1. Field of the Invention
The present invention relates to integrated circuit packages and, more particularly, to integrated circuit packages that are stackable.
2. Description of the Related Art
As the trend for memory integrated circuit (IC) packages to be smaller and their memory density to be larger continues, advancements in packaging integrated circuits are needed. One recent advancement involves stacking multiple integrated circuit dies within a single IC package. Such internal package stacking involves stacking a smaller die on a larger die. Each of the dies is wire bonded to a substrate. This type of stacking has, for example, been used with same function dies (e.g., two Flash memory dies) or different function dies (e.g., one Flash memory die and one SRAM die). Stacking of two or three dies has been done for stacked Chip Scale Packages (stacked CSP) and stacked Thin Small Outline Packages (TSOP).
Besides stacking of dies within a single IC package, IC packages can themselves be stackable. Conventionally, special connectors or modules are needed to stack integrated circuit packages. Unfortunately, however, the cost technologies. Accordingly, there is a need for improved stacking technologies for integrated circuit packages that are not dependent on special connectors or modules.